1. Technical Field
The present invention relates to systems for processing data and, more particularly, to systems employing a cache lock/unlock protocol for non-blocking caches.
2. Background Art
Microelectronic manufacturers are continually striving to improve the speed and performance of microprocessors and other processing devices, the performance of such devices being dependent upon many factors. One factor affecting the performance of a processor is the scheduling and execution of instructions associated with a piece of code executing on the processor. Many processors include an instruction decoder that decodes an instruction to create one or more micro-instructions, or micro-operations, that can be understood and executed by the processor. Micro-instructions and micro-operations will be referred to herein, in the singular, as a “μOP.” Micro-operations ready for execution are provided to a scheduler, which schedules the order of execution for a series of μOPs. Scheduled μOPs are then inserted into an execution stream and subsequently passed to execution circuitry for execution. A processor may also include a checker that determines whether a μOP has been properly executed. If a μOP has been properly executed, the μOP is retired. If the μOP did not properly execute, the μOP is sent into a replay loop, wherein the μOP is returned to the scheduler and rescheduled for execution.
Another factor affecting performance of microprocessors is the efficiency of the cache memory subsystem. One commonly-used method of increasing performance of cache memory subsystems is the implementation of a “non-blocking” or “out of order completion” cache mechanism, in which older requests for memory access, if they cannot be immediately serviced to completion, are “passed” by new requests that can complete sooner. The non-blocking cache mechanism determines which memory access requests can complete and which must wait. The non-blocking cache mechanism also provides a mechanism for permitting memory access requests to pass each other, and tracks the memory access requests as they complete out of order. A typical implementation of a non-blocking cache mechanism may use load request buffers (“LDRB's”) and store request buffers (“STRB's”) to track uncompleted memory requests.
Certain types of memory access requests do not support a non-blocking scheme. These types of requests require that there be no other reads or writes to the specified memory address until the requesting memory access instruction has completed execution. Such requests are “serialization events” because they require the processor to inhibit the non-blocking cache mechanism, and instead “lock” the cache, during execution of these instructions. In other words, strict ordering of the completion of requests is enforced for serialization events.
Embodiments of the cache lock apparatus and method disclosed herein address efficiency concerns and other issues related to serialization events in a non-blocking cache environment.